1. Field
Example embodiments relate generally to a duty cycle correction circuit, and more particularly to a duty cycle error accumulation circuit capable of precisely detecting duty cycle errors by accumulating the duty cycle errors for a plurality of periods and a duty cycle correction circuit having the same.
2. Description of the Related Art
Components, such as a processor and a memory included in a general electronic device, transceive data in synchronization with clock signals. However, errors may occur when the data are transceived between the components if a duty cycle error occurs due to a mismatch in length between a logic low level duration and a logic high level in the clock signal.
For instance, in the case of a double data rate (DDR) memory, the data are transceived at every rising edge and falling edge of the clock signal. If the duty cycle error occurs in the clock signal, a data transceiving interval may not be constantly maintained, so an error may occur when the data are transceived between the DDR memory and the processor.
Therefore, the duty cycle error of the clock signal has to be kept below a predetermined level for the normal operation of electronic devices.
Recently, as the clock frequency of the electronic device is gradually increased, an allowable value of the duty cycle error of the clock signal is also gradually reduced. Thus, a duty cycle correction circuit capable of precisely detecting the duty cycle error of the clock signal is necessary to correct the duty cycle error of the clock signal.